Measurement-computing CIO-PDMAxx Manuale Utente Scaricare il pdf (Pagina 19)

2. If word mode is selected for regular I/O (D2 = 1), then the B direction bit is

ignored. Both ports operate as a single 16-bit port with the direction set by A

direction bit D0.

3. The XFERSRC bit is used in both REP and DMA modes to select the transfer

clock source.

5.2.3 Interrupt Control Register

The interrupt Control Register is an 8-bit read/write register.

Base Address + 3

LSBMSB

SLOPEINT

SRC0

INT

SRC1

AUX3

000

INT

ENB

01234567

0 = + Edge 1 = - EdgeSLOPE0

00 = External Input

01 = 8237 Terminal Count

10 = Counter/Timer Terminal Count

11 = 8237 Terminal Count

INTSRC(1:0)2:1

Auxiliary user outputAUX33

0 = Disable, 1 = EnableINTENB7

DescriptionNameBit

Notes:

1. The Interrupt Control Register is cleared on power-up, thus disabling interrupts.

2. When REP_ENB bit is set, the Interrupt Source automatically defaults to the

Counter/Timer Terminal Count.

5.2.4 Counter Load & Read Registers Base Address + 4, 5, 6, and 7

Counter 0

Base Address + 4

LSBMSB

D0D1D2D3D4D5D6D7

01234567

Counter 1

Base Address + 5

LSBMSB

D0D1D2D3D4D5D6D7

01234567

Counter 2

Base Address + 6 LSB

D0D1D2D3D4D5D6D7

01234567

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 31 32

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