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2. If word mode is selected for regular I/O (D2 = 1), then the B direction bit is
ignored. Both ports operate as a single 16-bit port with the direction set by A
direction bit D0.
3. The XFERSRC bit is used in both REP and DMA modes to select the transfer
clock source.
5.2.3 Interrupt Control Register
The interrupt Control Register is an 8-bit read/write register.
Base Address + 3
LSBMSB
SLOPEINT
SRC0
INT
SRC1
AUX3
000
INT
ENB
01234567
0 = + Edge 1 = - EdgeSLOPE0
00 = External Input
01 = 8237 Terminal Count
10 = Counter/Timer Terminal Count
11 = 8237 Terminal Count
INTSRC(1:0)2:1
Auxiliary user outputAUX33
0 = Disable, 1 = EnableINTENB7
DescriptionNameBit
Notes:
1. The Interrupt Control Register is cleared on power-up, thus disabling interrupts.
2. When REP_ENB bit is set, the Interrupt Source automatically defaults to the
Counter/Timer Terminal Count.
5.2.4 Counter Load & Read Registers Base Address + 4, 5, 6, and 7
Counter 0
Base Address + 4
LSBMSB
D0D1D2D3D4D5D6D7
01234567
Counter 1
Base Address + 5
LSBMSB
D0D1D2D3D4D5D6D7
01234567
Counter 2
Base Address + 6 LSB
D0D1D2D3D4D5D6D7
01234567
15
- Revision 5 1
- September, 2000 1
- HM CIO-PDMA##.lwp 2
- This page is blank 4
- 1.0 INTRODUCTION 5
- 2.0 SOFTWARE INSTALLATION 6
- 3.0 HARDWARE INSTALLATION 6
- 3.3 WAIT STATE JUMPER 8
- 4.1 SIGNAL CONNECTIONS 9
- 5.0 REGISTER MAPS 12
- 5.2 CIO-PDMA32 REGISTER MAP 17
- BCDM0M1M2RL0RL1SC0SC1 20
- I0I1I2I3 21
- REP_DONEREP_FLGOVERRUNUNDER 21
- CommentsHALF_FF_CNT_REP_CONT 23
- DescriptionNameBit 23
- XXXXXXXX 24
- B0B1B2B3B4B5B6B7 24
- A0A1A2A3A4A5A6A7 24
- 6.0 SPECIFICATIONS 25
- Counter section 26
- Environmental 27
- For your notes 28
- EC Declaration of Conformity 31
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